1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit packaging.
2. Description of the Background Art
As is well known, an integrated circuit may be packaged to protect the integrated circuit from mechanical damage and contamination. A packaging process may involve encapsulation of an integrated circuit, deposition of a passivation layer on the integrated circuit, and/or sealing portions of the integrated circuit. For example, an optically transparent lid (e.g., glass) may be formed over a portion of an integrated circuit that is responsive to optical energy, such as light. Such optically transparent lids are employed in UV-erasable EPROM""s and imaging devices such as grating light valves, for example. Opaque lids, such as ceramic lids, may also be employed in other applications.
Because a packaging process may involve high temperature heating and flowing of materials, an integrated circuit may be damaged during packaging. For example, a crack may form in the substrate or passivation layer of an integrated circuit after flowing solder on a metal adhesion layer overlying the substrate. The crack may break the integrated circuit or render it unreliable. From the foregoing, a packaging technique that minimizes damage to integrated circuits is highly desirable.
In one embodiment, an integrated circuit packaging structure includes a first metal adhesion layer formed under a lid and a second metal adhesion layer formed over a substrate. The lid includes a free surface that may move a small amount without cracking. The second metal adhesion layer is configured such that its outer end does not extend past the free surface of the lid to minimize crack formation.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.